In the Call Stack window, you can see where the illegal access was made. In this example, invalid memory is accessed. Looking at the Register window, you can see that the NVIC:CFSR flag DIVBYZERO is set. In the Call Stack window, you can see the source code line where the invalid division occurred.
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This example shows how to catch division by zero errors, by enabling the DIV_0_TRP bit in the CCR register. In this specific case, it is very difficult to find the actual reason for the problem, because it has to do with a CPU running at an incorrect frequency. IMPRECISERR = 1 = Imprecise data access error has occurred.īecause the error is imprecise, it is not possible to see the address of the offending data access.
In the Register window, the NVIC:CFSR (Configurable Fault Status Register) shows that an imprecise data access error has occurred. In the Call Stack window, you can see which line of code that was executed when the HardFault occurred. This leads to HardFault exceptions at "random" places, at instructions that are normally valid. In this example, the CPU clock on a Cortex-M3 board has been set to a very high frequency. Discussionĭifferent fault scenarios are described in the examples below.
Typically, HardFault is used for unrecoverable system failures. HardFault refers to all classes of faults that cannot be handled by any of the other exception mechanisms. The purpose of this Technical Note is to show how HardFault errors can be debugged using IAR Embedded Workbench for Arm.